• DocumentCode
    1563863
  • Title

    GASTIM: A timing analyzer for GaAs digital circuits

  • Author

    Hernández, A. ; Gómez, L. ; Nunez, A.

  • Author_Institution
    CMA, Univ. de Las Palmas de Gran Canaria, Spain
  • fYear
    1993
  • Firstpage
    190
  • Lastpage
    195
  • Abstract
    A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15% error and with a speed-up of three orders of magnitude for several circuits tested as compared with HSPICE simulations
  • Keywords
    III-V semiconductors; computational complexity; delays; fault diagnosis; gallium arsenide; integrated circuit modelling; logic testing; timing; GASTIM; GaAs; delay time; digital circuits; overlapping input transitions; prototype timing analyzer; ratioed logic; timing analyzer; CMOS logic circuits; Delay; Digital circuits; Gallium arsenide; Logic circuits; Logic devices; MESFETs; Pulse inverters; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-4350-1
  • Type

    conf

  • DOI
    10.1109/EURDAC.1993.410636
  • Filename
    410636
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1563863