Efficient analysis of mixed-signal ASICs for smart sensors

Smart sensor systems usually contain highly integrated mixed-signal ASICs (application specific integrated circuits). The design of such a circuit typically falls into two distinct tasks: the development of a customized analog part and the design of an often custom-specific digital processor core. While the latter is likely to yield first time right silicon, the former usually requires more design iterations. To speed up the design process, independent optimization of both parts is desirable, but hardly possible in conventional designs. This paper proposes several measures to improve the prototyping and evaluation phase of a class of mixed-signal ASICs typical for smart sensors. Specifically, we suggest using a JTAG-like interface to disentangle analog and digital part and enable external data processing by means of an FPGA (field programmable gate arrays). Furthermore, we propose to replace the RAM/ROM blocks of a user-specific controller with a dual-ported RAM to achieve full programmability while at the same time preserving the overall architecture. Both approaches have successfully been used for the design of a smart sensor system for automotive applications.