An all-digital phase-locked loop compiler with liberty timing files

Author

Ching-Che Chung ; Duo Sheng ; Chen-Han Chen

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Min-Hsiung, Taiwan

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

4

Abstract

In this paper, an all-digital phase-locked loop (ADPLL) compiler with liberty timing files (.lib) is presented. The proposed digitally controlled oscillator (DCO) frequency range estimation algorithm can accurately compute the frequency range of the DCO with only liberty timing files. Therefore, the proposed ADPLL compiler can generate a wide frequency range and monotonic response DCO circuit according to the user input specifications. The generated DCO circuit is designed with standard cells. Thus, the design turnaround time for the ADPLL can be greatly reduced. The proposed ADPLL compiler is verified with SPICE circuit simulator. The maximum frequency estimation error is smaller than 5.92% in 90nm or 65nm CMOS processes.

Keywords

CMOS digital integrated circuits; circuit simulation; digital phase locked loops; phase locked oscillators; ADPLL compiler; CMOS processes; SPICE circuit simulator; all-digital phase-locked loop compiler; digitally controlled oscillator; frequency estimation error; frequency range estimation algorithm; liberty timing files; monotonic response DCO circuit; size 65 nm; size 90 nm; CMOS process; Computational modeling; Delays; Estimation; Frequency estimation; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2014.6834903

Filename

6834903