• DocumentCode
    156672
  • Title

    Advanced CMOS reliability challenges

  • Author

    Prasad, C.

  • Author_Institution
    Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA
  • fYear
    2014
  • fDate
    28-30 April 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.
  • Keywords
    CMOS integrated circuits; integrated circuit modelling; integrated circuit reliability; HK-MG; Trigate-FinFET; advanced CMOS reliability process; physical mechanism; size 65 nm to 22 nm; Aging; Degradation; FinFETs; Integrated circuit reliability; Logic gates; Optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
  • Conference_Location
    Hsinchu
  • Type

    conf

  • DOI
    10.1109/VLSI-DAT.2014.6834931
  • Filename
    6834931
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=156672