Double sampling architecture for performing fine time interpolation within a limited logic density FPGA

Based on the analysis for the requirement of the Field-Programmable Gate Array (FPGA) when the time interpolation time-to-digital converter (TDC) is planed to be applied in it, this paper describes a double sampling architecture for time interpolation TDC in the FPGA. The architecture extends the cover range of the delay-chain for twice, and can be implanted in those low-cost limited logic density FPGAs with high resolution. The prototype design employing Cyclone or Spartan 3E family device shows the least significant bit (LSB) of about 164 ps/83.3 ps and the root mean square (RMS) value for worst-case random error of about 94 ps/45.68 ps obtained.