A two-step dynamic reference A/D converter

In this paper, a novel 8-bit 100MS/s two-step dynamic reference analog-to-digital (A/D) converter architecture is proposed. Using a binary search algorithm, each voltage reference is dynamically controlled by all previous output bits. The offset-compensation and the pipelining techniques are employed to enhance performance. Since the number of comparators is the same as the intended bits of resolution, which ensures hardware simplicity, the proposed design can potentially achieve smaller chip area and lower power consumption than conventional high-speed ADC topologies.