• DocumentCode
    1568042
  • Title

    PAC duo system power estimation at ESL

  • Author

    Hsieh, Wen-Tsan ; Yeh, Jen-Chieh ; Huang, Shi-Yu

  • Author_Institution
    SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan
  • fYear
    2010
  • Firstpage
    815
  • Lastpage
    820
  • Abstract
    In this work, we develop an electronic system-level (ESL) power estimation framework which uses the specified power model interface. Using the proposed power model interface we can easily integrate the various power models in ESL virtual platform. Designers can choose either the coarse-grained or fine-grained power models according to the trade-off between accuracy and computing cost. The experimental results show the proposed method can accurate estimate the system power trend immediately compared with traditional method. We also demonstrated the capability of system power and performance analysis in both hardware-view and software-view by using our approach at ESL. Meanwhile, it can be used for high level architecture exploration directly.
  • Keywords
    parallel architectures; power aware computing; ESL virtual platform; PAC duo system power estimation; coarse-grained power models; electronic system-level power estimation; fine-grained power models; high level architecture exploration; parallel architecture core duo system; power model interface; Batteries; Costs; Electronics industry; Energy consumption; Engines; Frequency; Industrial electronics; Performance analysis; Phase estimation; Power system modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-5765-6
  • Electronic_ISBN
    978-1-4244-5767-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2010.5419777
  • Filename
    5419777