A single-chip MPEG/audio decoder LSI based on a compact decoding algorithm

Author

Iwadare, Masahiro ; Takano, Hideto ; Shibuya, Yoshitaka ; Sakamoto, Hideki ; Kuwajima, Takeshi ; Kitabatake, O. ; Kobayashi, Naoko

Author_Institution

Inf. Technol. Res. Labs., NEC Corp., Kawasaki, Japan

fYear

1995

Firstpage

118

Lastpage

125

Abstract

A single-chip decoder LSI is developed for audio bit-stream specified by ISO/IEC MPEG (the International Organisation for Standardisation/the International Electrotechnical Commission Moving Pictures Expert Group). The applicable layers are Layer I and II of MPEG-1 and MPEG-2/lower-sampling-frequency mode. To reduce on-chip memory for audio signal synthesis the LSI employs a fast calculation algorithm that was developed when the decoder was realized by signal processors. The reliability in bitstream synchronization is improved by checking bitstream inconsistency. Bitstream error concealment by repeating previous audio data is supported. The decoding delay is adjustable when connected with an optional external memory

Keywords

application specific integrated circuits; audio signals; decoding; large scale integration; multimedia communication; synchronisation; video signal processing; ISO/IEC MPEG; LSI; Layer I; Layer II; MPEG-1; MPEG-2/lower-sampling-frequency mode; audio bit-stream; audio signal synthesis; bitstream error concealment; bitstream inconsistency; bitstream synchronization; compact decoding algorithm; decoding delay; optional external memory; single-chip MPEG/audio decoder; Bit rate; Decoding; Frequency synchronization; IEC standards; ISO standards; Large scale integration; MPEG standards; National electric code; Signal processing algorithms; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]

Conference_Location

Sakai

Print_ISBN

0-7803-2612-1

Type

conf

DOI

10.1109/VLSISP.1995.527483

Filename

527483