A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms

Author

Alioto, M. ; Poli, M. ; Rocchi, S. ; Vignoli, V.

Author_Institution

Dipt. di Ing. dellInf., Univ. di Siena, Rome

fYear

2007

Firstpage

368

Lastpage

371

Abstract

In this paper, a model of the bus power consumption able to predict the results of a multi-bit differential power attack (DPA) in symmetric-key cryptographic algorithm (e.g. AES, DES) is developed. The analytical results represent a theoretical basis to better understand the vulnerability to DPA attacks of cryptographic VLSI circuits. To the best of the authors´ knowledge, this is the first paper that quantitatively evaluates the fundamental parameters that determine the effectiveness of DPA attacks to symmetric-key algorithms. The results are validated by means of SPICE simulations on the address bus of a MIPS32 architecture in a 0.18-mum CMOS technology, with the MIPS32 being modeled by an in-house cycle-accurate simulator.

Keywords

CMOS integrated circuits; VLSI; public key cryptography; CMOS technology; MIPS32 architecture; SPICE simulations; bus power consumption; cryptographic VLSI circuits; in-house cycle-accurate simulator; multibit differential power attack; symmetric-key cryptographic algorithms; Algorithm design and analysis; CMOS technology; Circuit simulation; Cryptography; Data security; Energy consumption; Predictive models; SPICE; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on

Conference_Location

Seville

Print_ISBN

978-1-4244-1341-6

Electronic_ISBN

978-1-4244-1342-3

Type

conf

DOI

10.1109/ECCTD.2007.4529609

Filename

4529609