Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement

In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90 nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.