• DocumentCode
    1569520
  • Title

    A versatile recognition processor for sensor network applications

  • Author

    Takashima, Risako ; Hanai, Yuya ; Hori, Yuichi ; Kuroda, Tadahiro

  • Author_Institution
    Keio Univ., Yokohama, Japan
  • fYear
    2010
  • Firstpage
    349
  • Lastpage
    350
  • Abstract
    A versatile recognition processor is presented that comprises 2.1M transistors using a 90 nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.
  • Keywords
    CMOS integrated circuits; acoustic signal detection; image recognition; microprocessor chips; nanoelectronics; video signal processing; CMOS technology; Haar-like feature; acceleration signals; cascaded classifier; image detection; image recognition; optimal architecture design; power efficiency; sensor network applications; sound detection; transistors; versatile recognition processor; video detection; Acceleration; Acoustic sensors; CMOS technology; Circuits; Degradation; Energy consumption; Hafnium; Image recognition; Random access memory; Wearable sensors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-5765-6
  • Electronic_ISBN
    978-1-4244-5767-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2010.5419867
  • Filename
    5419867
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1569520