Functional-level synthesis with VHDL

The authors describe a procedure and a tool for ASIC synthesis with VHDL. They show that the functional level which they define and use as the design input provides a synthesis level located between the system-level synthesis and the RT-level synthesis. The described design and synthesis process is based on a complete methodology and the use of its functional model allows designers to describe their solutions according to two views: an organizational view which defines the internal structure, and a behavioral view which describes the activity of each function. Tools, mainly graphical, have been developed as an aid to capture the design description. After that, a generator is used to obtain the complete VHDL model at a RT-level model which is simulatable and synthesizable. Such a tool leads to obtaining of ASIC prototypes efficiently and in an incremental manner. Results for some ASICs designed by the authors are given to illustrate the benefit of the proposed method and the significance of the functional level