Technique for controlling power-mode transition noise in distributed sleep transistor network

Power gating technique is one of the effective technologies to achieve both low leakage and high performance in circuits. This work focuses on considering power-mode transition noise (i.e., ground noise) in power gated circuit design. So far, even though satisfying the limit of power-mode transition noise is an important design constraint, not many works have seriously addressed it as yet, just simply sacrificing the wakeup delay to meet the constraint by turning on the sleep transistors sequentially one by one. In this work, we analyze how the switching current affects the size of sleep transistors, from which how the power-mode transition noise can be mitigated by controlling the power-up sequence of sleep transistors, and propose a systematic solution to the problem of integrating the power-up controlling of sleep transistors into the power gated design flow in distributed sleep transistor network to take into account power-mode transition noise constraint as well as performance loss constraint. Through experiments with ISCAS benchmarks, it is confirmed that under the same power-mode transition noise constraint, our proposed solution is able to reduce the wakeup delay by 23% - 51% compared to the designs produced by a previous power gated design technique.