A 75GHz PLL Front-End Integration in 65nm SOI CMOS Technology

Author

Kim, Daeik ; Kim, Jonghae ; Plouchart, Jean-Olivier ; Cho, Choongyeun ; Lim, Daihyun ; Li, Weipeng ; Trzcinski, Robert

fYear

2007

Firstpage

174

Lastpage

175

Abstract

A 75GHz PLL front-end, composed of complementary LC VCO, a buffer with AC coupling, and a static CML latch divider, is integrated in 65 nm SOI CMOS technology. The circuitry is developed with milli-meter wave link specifications, technology consideration, process variation, and topology selections. The PLL front-end achieves 5.9% tuning range centered at 73.4GHz and free-running phase noise of -1 lOdBc/Hz at 10MHz offset with 71mW.

Keywords

CMOS integrated circuits; current-mode logic; flip-flops; millimetre wave integrated circuits; phase locked loops; phase noise; silicon-on-insulator; voltage-controlled oscillators; AC coupling; PLL front-end integration; SOI CMOS technology; Si-SiO₂; complementary LC VCO; free-running phase noise; frequency 10 MHz; frequency 73.4 GHz; frequency 75 GHz; latch divider; millimeter wave link specifications; power 71 mW; size 65 nm; static CML; CMOS technology; Circuit optimization; Frequency conversion; Latches; Phase locked loops; Phase noise; Silicon on insulator technology; Tail; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342703

Filename

4342703