DocumentCode
1570407
Title
4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS
Author
Anuar, Nazrul ; Takahashi, Yasuhiro ; Sekine, Toshikazu
Author_Institution
Grad. Sch. of Eng., Gifu Univ., Gifu, Japan
fYear
2009
Firstpage
65
Lastpage
68
Abstract
This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.
Keywords
CMOS logic circuits; VHF circuits; adders; carry logic; 2PASCL circuit technology; frequency 10 MHz to 100 MHz; ripple carry adder; static CMOS RCA; two-phase clocked adiabatic static CMOS logic; CMOS logic circuits; Clocks; Diodes; Energy consumption; Energy dissipation; Logic circuits; Power supplies; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location
Antalya
Print_ISBN
978-1-4244-3896-9
Electronic_ISBN
978-1-4244-3896-9
Type
conf
DOI
10.1109/ECCTD.2009.5274985
Filename
5274985
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