• DocumentCode
    1570785
  • Title

    2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications

  • Author

    Chen, Tung-Chien ; Chen, Yu-Han ; Tsai, Chuan-Yung ; Tsai, Sung-Fang ; Chien, Shao-Yi ; Chen, Liang-Gee

  • Author_Institution
    Nat. Taiwan Univ., Taipei
  • fYear
    2007
  • Firstpage
    222
  • Lastpage
    223
  • Abstract
    A 2.8 to 67.2 mW H.264 encoder is implemented on a 12.8 mm2 die with 0.18 mum CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.
  • Keywords
    CMOS integrated circuits; code standards; low-power electronics; motion estimation; parallel architectures; video coding; CMOS technology; content-aware algorithms; flexible system hierarchy; mobile applications; module-wise gated clock; parallel architectures; power 2.8 mW to 67.2 mW; power-aware H.264 encoder; CMOS technology; Control systems; Energy consumption; Engines; Filters; Motion estimation; Parallel architectures; Pipeline processing; Processor scheduling; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-900784-05-5
  • Electronic_ISBN
    978-4-900784-05-5
  • Type

    conf

  • DOI
    10.1109/VLSIC.2007.4342727
  • Filename
    4342727
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1570785