DocumentCode
1570836
Title
Lowering the Quantum Gate Cost of Reversible Circuits
Author
Miller, D. Michael ; Sasanian, Zahra
Author_Institution
Dept. of Comput. Sci., Univ. of Victoria, Victoria, BC, Canada
fYear
2010
Firstpage
260
Lastpage
263
Abstract
One approach to determining a quantum circuit is to first synthesize a circuit composed of binary reversible gates and to then map that circuit to an equivalent quantum gate realization. This paper considers the mapping phase with the goal of reducing the number of quantum gates required. Our method is based on novel line labeling and gate moving procedures. Results are presented for the quantum library: NOT, controlled-NOT, and the square-root-of-NOT gates (V and V+). The approach is applicable to other quantum gate libraries.
Keywords
network synthesis; quantum gates; binary reversible gates; circuit synthesis; controlled-NOT gate; gate moving; line labeling; mapping phase; quantum circuit; quantum gate cost; quantum gate library; reversible circuit; square-root-of-NOT gate; Boolean functions; Circuit synthesis; Computer science; Costs; Feedback; Labeling; Libraries; Optimization methods; Quantum computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location
Seattle, WA
ISSN
1548-3746
Print_ISBN
978-1-4244-7771-5
Type
conf
DOI
10.1109/MWSCAS.2010.5548653
Filename
5548653
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