A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

Author

Chang, Leland ; Nakamura, Yutaka ; Montoye, Robert K. ; Sawada, Jun ; Martin, Andrew K. ; Kinoshita, Kiyofumi ; Gebara, Fadi H. ; Agarwal, Kanak B. ; Acharyya, Dhruva J. ; Haensch, Wilfried ; Hosokawa, Kohji ; Jamse, Damir

Author_Institution

IBM, Yorktown Heights

fYear

2007

Firstpage

252

Lastpage

253

Abstract

A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.

Keywords

CMOS memory circuits; SRAM chips; arrays; cache storage; field effect MMIC; LSDL decoder; SRAM; SRAM cell stability; array efficiency; design tradeoffs; frequency 295 MHz; frequency 5.3 GHz; gated diode sense amplifier; high-speed caches; single-supply operation down; size 65 nm; variability tolerance; voltage 0.41 V; voltage 1.2 V; Clocks; Decoding; Diodes; Driver circuits; Logic arrays; Low voltage; Random access memory; Stability; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342739

Filename

4342739