An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

Author

Morita, Yasuhiro ; Fujiwara, H. ; Noguchi, Hiroki ; Iguchi, Yoshinori ; Nii, Koji ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko

Author_Institution

Kobe Univ., Kobe

fYear

2007

Firstpage

256

Lastpage

257

Abstract

This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment.

Keywords

SRAM chips; integrated circuit design; low-power electronics; voltage control; DVS; SRAM design; dynamic voltage scaling; highly-integrated SRAM; memory cell; size 45 nm; size 90 nm; storage capacity 64 Mbit; threshold-voltage variation; voltage 0.42 V; voltage-control scheme; write-back scheme; Degradation; Driver circuits; Dynamic voltage scaling; Electronic equipment testing; Low voltage; Random access memory; Read-write memory; Very large scale integration; Virtual colonoscopy; Voltage control; 8T; DVS; SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342741

Filename

4342741