DocumentCode
1571051
Title
A CMOS ΔΣ fractional-n frequency synthesizer with quantization noise pushing technique
Author
Yang, Yu-Che ; Lu, Shey-Shi
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
Firstpage
262
Lastpage
263
Abstract
A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18 mum CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15 dB with this technique. The power consumption is 26.8mW from a 2V supply.
Keywords
CMOS integrated circuits; delta-sigma modulation; frequency synthesizers; integrated circuit noise; phase locked loops; phase noise; ΔΣ modulator; CMOS ΔΣ fractional-N frequency synthesizer; CMOS technology; in-band phase noise; out-band phase noise; power 26.8 mW; quantization noise pushing technique; size 0.18 mum; voltage 2 V; Circuits; Frequency control; Frequency synthesizers; Noise reduction; Phase frequency detector; Phase locked loops; Phase modulation; Phase noise; Quantization; Tellurium; ΔΣ; frequency synthesizer and phase-locked loops; quantization noise;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-04-8
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342743
Filename
4342743
Link To Document