Polychrony for formal refinement-checking in a system-level design methodology

The productivity gap incurred by the rising complexity of system-on-chip design have necessitated newer design paradigms to be introduced based on system-level design languages. A gating factors for widespread adoption of these new paradigms is a lack of formal tool support of refinement based design. A system level representation may be refined manually (in absence of adequate behavioral synthesis algorithms and tools) to obtain an implementation, but proving that the lower level representation preserves the correctness proved at higher level models is still an unsolved problem. We address the issue of formal refinement proofs between design abstraction levels using the concepts of polychronous design. Refinement of synchronous high-level designs into globally asynchronous and locally synchronous architectures is formally supported in this methodology. The polychronous (i.e. multiclocked) model of the SIGNAL design language offers formal support for the capture of behavioral abstractions for both very high-level system descriptions (e.g. SYSTEMC/SPEcC,) and behavioral-level IP components (e.g. VHDL). Its platform, polychrony, provides models and methods for a rapid, refinement-based, integration and a formal conformance-checking of GALS hardware/software architectures. We demonstrate the effectiveness of our approach by the experimental, comparative, case study of an even-parity checker design in SPEcC. It highlights the benefits of the formal models, methods and tools provided in polychrony, in representing functional, architectural, communication and implementation abstractions of the design, and the successive refinements.