Fast arithmetic error feedback circuits for digital filters with shift operation circuits and shared multiplier

In this paper, we propose a fast arithmetic error feedback (EF) structure with shift operation circuits and shared multiplier. For optimization of EF network, we show the design method based on the Lagrange multiplier method for designing the shared multiplier and the branch and bound based algorithm for optimization of the shift operation circuits. The branch and bound method can reduce the calculation cost because the sub-trees can be cut based on the lower bound estimation. Finally, we present a numerical example by designing the EF with shift operation circuits and shared multiplier. From the results, we demonstrate the effectiveness of the proposed method and show the calculation time is a few seconds.