Modelling of a self timed dataflow processor in VHDL

Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989). Dataflow computers differ from most other parallel architectures. They are based on the concept of data-driven computation instead of the program store computation model. Since the data-driven computation model provides the execution of instructions asynchronously, it is natural to implement a dataflow processor using self-timed circuits. The authors present the design of a static dataflow processor implemented using self-timed circuits. They use VHDL to model part of the design to aid the simulation and verification process