• DocumentCode
    157540
  • Title

    Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

  • Author

    Kasapaki, E. ; SparsØ, Jens

  • Author_Institution
    Dept. of Appl. Math. & Comput. Sci., Tech. Univ. of Denmark, Lyngby, Denmark
  • fYear
    2014
  • fDate
    12-14 May 2014
  • Firstpage
    45
  • Lastpage
    52
  • Abstract
    In this paper we explore the use of asynchronous routers in a time-division-multiplexed (TDM) network-on-chip (NOC), Argo, that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either synchronous or mesochronous. We use asynchronous routers to achieve a simpler, smaller and more robust, self-timed design. Our design exploits the fact that pipelined asynchronous circuits also behave as ripple FIFOs. Thus, it avoids the need for explicit synchronization FIFOs between the routers. Argo has interesting elastic timing properties that allow it to tolerate skew between the network interfaces (NIs). The paper presents Argo NOC-architecture and provides a quantitative analysis of its ability of absorb skew between the NIs. Using a signal transition graph model and realistic component delays derived from a 65 nm CMOS implementation, a worst-case analysis shows that a typical design can tolerate a skew of 1-5 cycles (depending on FIFO depths and NI clock frequency). Simulation results of a 2 × 2 NOC confirm this.
  • Keywords
    CMOS digital integrated circuits; Petri nets; asynchronous circuits; delays; integrated circuit design; integrated circuit modelling; multiprocessing systems; network-on-chip; synchronisation; time division multiplexing; Argo NOC-architecture; CMOS process; NIs; TDM-based NOC designs; asynchronous routers; common time reference; elastic timing property; explicit synchronization FIFOs; hard real-time systems; multiprocessor platform; network interfaces; network-on-chip; pipelined asynchronous circuits; realistic component delays; ripple FIFOs; self-timed design; signal transition graph model; size 65 nm; time-elastic time-division-multiplexed NOC; Clocks; Latches; Nickel; Pipelines; Synchronization; Time division multiplexing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asynchronous Circuits and Systems (ASYNC), 2014 20th IEEE International Symposium on
  • Conference_Location
    Potsdam
  • ISSN
    1522-8681
  • Type

    conf

  • DOI
    10.1109/ASYNC.2014.14
  • Filename
    6835810