Synthesis of QDI FSMs from Synchronous Specifications

Quasi-Delay insensitive (QDI) circuits are the most robust and practical that can be built and are resilient to process, temperature and voltage (PVT) variations. Although there are many research papers that can translate synchronous designs into asynchronous sequential designs, to the best of our knowledge, there is neither QDI finite state machine (FSM) models proposed nor algorithms or tools designed. Three QDI FSM (QFSM) designs (i.e. NCLD, NCLX and ROC QFSMs) are proposed and an algorithm to automatically synthesize QFSMs from synchronous FSM specifications in Verilog is designed and implemented in Java. One of the distinguish feature is that the behaviors of our QFSMs are the same as those of the corresponding synchronous FSMs in terms of functionality. This greatly simplifies the verification complexity and reduces verification cost. Two sets of FSM circuits (i.e. verifiable benchmark circuits and ISCAS89) are exploited to carry out verification and performance evaluation. The experimental results show that ROCopt QFSMs use the least hardware cost and consume lowest energy in average.