A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design

This paper proposes a new transistor topology to design gates required by Null Convention Logic for low voltage operation. The new topology enables implementing all functionalities required by this design style. Extensive simulation results conducted in a 65 nm CMOS technology allow comparing the new topology to popular static and semi-static ones and indicate that the former presents better speed, energy and leakage trade-offs for different voltage levels, demonstrating the suitability of the new topology for low voltage applications. Drawbacks are an area of 4 minimum size transistors and reduced robustness against soft errors, when operating at non-minimum voltages.