Domino logic based high speed dynamic comparator

Comparator is basic building block for designing of the present analog and mixed signal (AMS) systems. Speed and Power are two major factors which are essential for high speed applications. In this paper, we present the analysis of existing clocked regenerative comparators in terms of power, speed and slew rate. A new clocked regenerative comparator is with domino logic proposed which exhibits better performance than the existing comparators and transient response of these comparators were plotted. The presented designs are simulated using 130nm CMOS Mentor Graphics tools.