High performance CMOS dual-modulus prescaler using selective latch technique

Author

Kim, Se-Yeob ; Lee, Soon-Seob ; Kim, Soo-Won ; Kim, Tae-Geun

Author_Institution

Dept. of Electron. Eng., Korea Univ., Seoul, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

321

Lastpage

324

Abstract

This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption

Keywords

CMOS digital integrated circuits; SPICE; UHF integrated circuits; circuit simulation; high-speed integrated circuits; integrated circuit layout; low-power electronics; mobile communication; prescalers; 0.35 mum; 2.6 GHz; 2.7 V; 22.6 mW; CMOS dual-modulus prescaler; HSPICE; RF mobile communication systems; asynchronous architecture; control signal immunity; dual mode division ratio; full speed operating flip-flops; high speed operation; logic gates; maximum operating frequency; power supply; propagation delay; pulse swallow method; reduced power consumption; selective latch technique; simulation results; CMOS logic circuits; CMOS technology; Communication system control; Energy consumption; Error correction; Flip-flops; Logic gates; Mobile communication; Propagation delay; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820919

Filename

820919