DocumentCode
1576695
Title
A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors
Author
Kim, Jin-Cheon ; Lee, Sang-Hoon ; Park, Hong-June
Author_Institution
Dept. of Electr. Eng., POSTDCH, Pohang, South Korea
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
384
Lastpage
387
Abstract
In this paper, a sense amplifier-based flip-flop (SAFF) with a fast output transition capability is proposed to reduce the pipeline overhead of high-performance microprocessors. The new SAFF overcomes the speed limitation of the conventional SAFF which is caused by the output latch implementation. The speed enhancement is achieved by reducing the number of gate stages to be passed from three to two. The SPICE simulation shows that the clock-to-output delay time of the new SAFF is enhanced by 63% compared to that of the conventional SAFF and the new SAFF has the fastest speed in comparison with the recently published flip-flops
Keywords
CMOS logic circuits; SPICE; flip-flops; microprocessor chips; CMOS SAFF; SPICE simulation; clock-to-output delay time; microprocessor; output transition time; sense amplifier-based flip-flop; Clocks; Delay; Energy consumption; Flip-flops; Latches; Logic design; Microprocessors; Pipelines; SPICE; Strontium;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5727-2
Type
conf
DOI
10.1109/ICVC.1999.820938
Filename
820938
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