Parameter-driven data path VHDL model generation for ASIC design

Previous methods for automatic generation of behavioral VHDL models require an ASIC engineer to have knowledge of particular input techniques such as graphical entry, specialized table, etc. The author presents a new method that takes the user-specified engineering parameters as inputs for the behavioral VHDL model generation. Since it is a common practice for the ASIC engineer to specify circuits using engineering parameters, this parameter-driven method allows an engineer to create a VHDL model quickly and easily. In addition, unlike the previous methods, the proposed method covers a wide range of circuits, including MSI circuits as well as FSM and CMB