Implementing a timing shell for VHDL simulation using the proposed EIA-567 standard

Timing issues in VHDL simulation continue to be important to the VHDL community. The proposed EIA-567 standard is one of several methods of describing a database for timing parameters within the language. Although there are several methods for accessing and using these data, the author explains how a particular timing shell was constructed, how it is used, its unique language constructs, and some singificant benefits of using this implementation