DocumentCode
1579173
Title
Accuracy of yield impact calculation based on kill ratio
Author
Ono, Makoto ; Iwata, Hisafumi ; Watanabe, Kenji
Author_Institution
Production Eng. Res. Lab., Hitachi Ltd., Kanagawa, Japan
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
87
Lastpage
91
Abstract
We evaluated the accuracy of yield impact calculations based on kill ratio analysis. The accuracy was calculated using computer simulated defect maps and bin maps. The results show that the yield impact was inaccurate when parametric faults caused low yield or a large number of non-killer defects were included in inspection reports. It is therefore recommended to evaluate bin maps and reduce the non-killer defects before calculating the yield impact.
Keywords
inspection; integrated circuit yield; bin map; computer simulation; defect map; in-line inspection; kill ratio analysis; nonkiller defect; parametric fault; semiconductor manufacturing; yield enhancement; yield impact; Accuracy; Circuit faults; Circuit testing; Computational modeling; Computer simulation; Equations; Inspection; Integrated circuit yield; Production engineering; Semiconductor device manufacture;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop
Print_ISBN
0-7803-7158-5
Type
conf
DOI
10.1109/ASMC.2002.1001580
Filename
1001580
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