Delay fault ATPG for F-scannable RTL circuits

Today´s digital circuits demand both high speed performance and miniaturization of chip size. As a result, delay fault testing has become very important to verify the quality requirements of VLSI chips. Full scan has been used to generate test patterns that achieves high fault coverage, of which the standard techniques for delay scan testing are skewed-load and broad-side. However, as the circuits become larger, using full scan can be very costly due to high area overhead and long test application time. In this paper, we apply delay fault automatic test pattern generation (ATPG) on F-scannable circuits. In our previous work, we have shown the strengths of F-scan compared with full scan in terms of area overhead, test application time, and fault coverage. We utilize the advantages of F-scan to solve the current problems of skewed-load and broad-side. The proposed method is to utilize a hybrid model for F-scannable circuits in generating test patterns, wherein a fast scan enable signal used by skewed-load technique is not required. Transition delay fault coverage achieved by this approach is equal to or higher than that achieved by both skewed-load and broadside approaches for gate-level full scan. This is proven through our experiments on ITC´99 benchmark circuits.