DocumentCode
1581206
Title
Processor Functional Test Generation - Some Results with Using of Genetic Algorithms
Author
Hudec, Ján
Author_Institution
Fac. of Inf. & Inf. Technol., Slovak Univ. of Technol., Bratislava, Slovakia
fYear
2011
Firstpage
159
Lastpage
160
Abstract
This contribution presents some results in the design and implementation of an universal functional test generator for VLSI circuits, such as microprocessor and processor cores. Our approach to test generation - the functional test generation method - is based on knowledges of instruction set architecture (ISA), functional description of VLSI systems at functional VHDL level and promising concept of software-based self test (SBST), for better test generation the genetic algorithm (GA) properties based on evolutionary strategiesw are used. The algorithm for automatic generation of test (normal executable test sequence of instructions) and arrangement, is used in very flexible and effective tool - Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction testing mixes is discussed.
Keywords
VLSI; automatic test pattern generation; automatic test software; electronic engineering computing; genetic algorithms; VHDL; VLSI circuits; automatic functional test generator; genetic algorithms; instruction set architecture; microprocessor; processor cores; processor functional test generation; software-based self test; universal functional test generator; Circuit faults; Feedback loop; Generators; Genetic algorithms; Microprocessors; Testing; Very large scale integration; VLSI functional testing; processor functional test generation; test simulation and verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Engineering of Computer Based Systems (ECBS-EERC), 2011 2nd Eastern European Regional Conference on the
Conference_Location
Bratislava
Print_ISBN
978-1-4577-0683-7
Electronic_ISBN
978-0-7695-4418-2
Type
conf
DOI
10.1109/ECBS-EERC.2011.37
Filename
6037534
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