Multicore energy reduction utilizing canary FF

MultiCore Processor System-on-Chip (MPSoC) is one of the promising technique to satisfy computing demands of the future consumer devices. While MPSoC has an advantage in energy consumption in comparison with high-frequency microprocessor-based system, it is still threatened by increasing energy consumption due to process-voltage-temperature (PVT) variations. It requires large design margins in the supply voltage, resulting in large energy consumption. This paper proposes to utilize a dual-sensing flip-flop (FF), named Canary FF, in order to reduce the overestimated voltage margin. We adopt canary FF to an MPSoC based on Toshiba´s MeP and estimate its energy reduction by cycle-based simulations. We find 20.5% energy reduction.