Error rate decrease through Hamming weight change for NAND Flash

NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory´s characteristic. According to the Flash memory mechanism, 0´s error is more likely to happen than 1´s error. The proposed error control code counts the number of `1´ in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.