DocumentCode
1584119
Title
Multi-level decision feedback equalization with clock recovery
Author
Kenney, Jack
Author_Institution
Dept. of Electron. Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fYear
1992
Firstpage
945
Abstract
Analytical expressions are developed to describe the dynamic response of the phase detector in multilevel decision feedback equalization (MDFE). First, it is shown that high density recording channels using a 2/3(1,7) run-length code are bandlimited, so that the Nyquist sampling criterion is satisfied. Consequently, the phase-locked loop (PLL) can be analyzed using sin x /x interpolation between samples of the equalized response. Analytical expressions are derived for determining the gain of the phase detector for MDFE, when the PLL uses a stochastic gradient algorithm. However, this approach is not attractive from an implementation standpoint. A simpler strategy in which the timing phase is only updated on certain signal trajectories is presented. The cost of using this simpler phase detector is timing jitter
Keywords
clocks; digital storage; equalisers; feedback; interpolation; phase-locked loops; 2/3(1,7) run-length code; Nyquist sampling criterion; clock recovery; dynamic response; equalized response; high density recording channels; multilevel decision feedback equalization; phase detector; phase-locked loop; signal trajectories; sin x/x interpolation; stochastic gradient algorithm; timing jitter; timing phase; Algorithm design and analysis; Clocks; Decision feedback equalizers; Detectors; Interpolation; Phase detection; Phase locked loops; Sampling methods; Stochastic processes; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
0-8186-3160-0
Type
conf
DOI
10.1109/ACSSC.1992.269081
Filename
269081
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