• DocumentCode
    1587816
  • Title

    Pipelining of digit-serial processing elements in recursive digital filters

  • Author

    Karlsson, Magnus ; Vesterbacka, Mark ; Kulesza, Wlodek

  • Author_Institution
    University of Kalmar
  • fYear
    2004
  • Firstpage
    129
  • Lastpage
    132
  • Keywords
    Adders; Arithmetic; Circuits; Clocks; Delay; Digital filters; Energy consumption; Lattices; Pipeline processing; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Symposium, 2004. NORSIG 2004. Proceedings of the 6th Nordic
  • Conference_Location
    Espoo, Finland
  • Print_ISBN
    951-22-7065-X
  • Type

    conf

  • Filename
    1344540
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1587816