Exact computation of the entropy of a logic circuit

Computing the entropy of a digital circuit has proved to be very useful for several applications in the area of VLSI system design. Recently, a method for entropy calculation has been used in the context of power estimation for logic circuits described at the register-transfer level. The technique has shown to be reasonably effective concerning the trade-off between the accuracy of the estimates produced and the execution time. However, the assumptions required to make the computation feasible are such that the obtained results are approximate. In this paper, we propose a symbolic algorithm for the exact calculation of the entropy of a logic circuit which is able to handle reasonably large examples without introducing any approximation. We present experimental data on standard benchmark designs in order to show the effectiveness of the new method; in addition, we compare our results to the ones obtained with the approximate approach. As a result, we observe a marginal penalty in the performance of the symbolic procedure; on the other hand, accuracy in the calculation increases significantly