Low voltage techniques for sub 100nm CMOS, RF transceivers

Author

Soumyanath, K.

Author_Institution

Commun. Circuits Lab., Intel Corp., Hillsboro, OR, USA

fYear

2005

Firstpage

501

Lastpage

504

Abstract

Sub 100 nm CMOS provides high f_T and f_max devices that offer many advantages for RFIC design. However, these benefits come with the necessity of using low supply voltages (∼1.2 V) and low resistivity substrates. In this paper, we describe circuit techniques for WLAN components (LNAs, synthesizers, filters and ADC front ends) that overcome these constraints while fully realizing the advantages of scaled CMOS.

Keywords

CMOS integrated circuits; frequency synthesizers; integrated circuit design; low-power electronics; radiofrequency amplifiers; radiofrequency filters; radiofrequency integrated circuits; transceivers; voltage-controlled oscillators; wireless LAN; 1.2 V; 100 nm; ADC front ends; CMOS RF transceivers; LNA; RFIC; VCO; WLAN components; filters; low resistivity substrates; low supply voltage design techniques; scaled CMOS; synthesizers; CMOS technology; Charge pumps; Circuits; Costs; Low voltage; Low-noise amplifiers; Radio frequency; Synthesizers; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8983-2

Type

conf

DOI

10.1109/RFIC.2005.1489857

Filename

1489857

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1589825