• DocumentCode
    1589855
  • Title

    Reliability evaluation of GaAs HBT technologies

  • Author

    Maneux, C. ; Labat, N. ; Malbert-Saysset, N. ; Touboul, A. ; Danto, Y. ; Dumas, J.-M. ; Riet, M. ; Scavennec, A.

  • Author_Institution
    ENSERB, Bordeaux I Univ., Talence, France
  • fYear
    1999
  • fDate
    6/21/1905 12:00:00 AM
  • Firstpage
    81
  • Lastpage
    86
  • Abstract
    This work describes the implementation of an experimental procedure to evaluate the reliability of Heterojunction Bipolar Transistors (HBT) on a GaAs substrate. It is based on the separation of ageing test accelerating factors applied to HBTs and TLM (“Transmission Line Model”) structures associated with emitter base and collector layers. Three different technological manufacturing processes are investigated : AlGaAs/GaAs double-mesa HBT, GaInP/GaAs self-aligned HBT and GaInP/GaAs fully planar HBT. HBTs submitted to combined bias and temperature stresses exhibit either a degradation of the SiN/GaAs interface correlated with the increase of the emitter-base leakage current and/or a detachment of Ge/Mo/W emitter ohmic contact related to the base and collector current decrease for high level injection in the forward regime. These investigations have assessed that GaInP over the extrinsic base acts as a better passivation layer than the conventional SiN does
  • Keywords
    III-V semiconductors; ageing; failure analysis; gallium arsenide; heterojunction bipolar transistors; leakage currents; life testing; passivation; semiconductor device reliability; semiconductor device testing; AlGaAs-GaAs; AlGaAs-GaAs double-mesa HBT; GaAs; GaAs HBT technologies; GaAs substrate; GaInP passivation layer; GaInP-GaAs; GaInP-GaAs fully planar HBT; GaInP-GaAs self-aligned HBT; Ge-Mo-W; Ge/Mo/W emitter ohmic contact; SiN passivation layer; SiN-GaAs; SiN-GaAs interface; TLM structures; ageing test accelerating factors; bias stresses; contact detachment; emitter-base leakage current; heterojunction bipolar transistors; manufacturing processes; reliability evaluation; temperature stresses; transmission line model structures; Accelerated aging; Degradation; Gallium arsenide; Heterojunction bipolar transistors; Life estimation; Manufacturing processes; Silicon compounds; Stress; Temperature; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Electron Devices for Microwave and Optoelectronic Applications, 1999. EDMO. 1999 Symposium on
  • Conference_Location
    London
  • Print_ISBN
    0-7803-5298-X
  • Type

    conf

  • DOI
    10.1109/EDMO.1999.821464
  • Filename
    821464