Improvement of electrical characteristics in LDMOS by the insertion of PBL and gate extended field plate technologies

This article provides a fabricating method to improve significantly both of the breakdown voltage and specific on-resistance in high resistivity drift region LDMOS using by both of the PBL doping under the source terminal and the gate extended field plate technologies. The insertion of PBL aims at the reduction of bulk current caused by the impact-ionization-generated holes while the gate extended field plate were be used to shift the impact ionization region from N-drift region surface near the gate side down toward the junction between the P-body and N-drift region to increase the breakdown voltage due to the increase of maximum depletion in the N-drift region.