Effect of oxide thickness on 32nm Pmosfet reliability

Author

Hadi, D. Abd ; Hatta, S. F Wan Muhamad ; Soin, N.

Author_Institution

Dept. of Electr. Eng., Univ. of Malaya, Kuala Lumpur, Malaysia

fYear

2010

Firstpage

244

Lastpage

247

Abstract

Negative Bias Temperature Instability (NBTI) has become one of the critical reliability concerns as scaling down CMOS technology especially on the pMOSFET device. A simulation study had been conducted on 32 nm conventional pMOSFET using the technology CAD (TCAD) Sentaurus Synopsys simulator tool. In this paper, the effects of the gate oxide thickness together with drain bias variations on the NBTI are studied. The effect on the device parameters such as interface traps concentration (N_it), threshold voltage (V_th) and drain current (I_d) degradation had been investigated and explained in detail.

Keywords

MOSFET; circuit CAD; semiconductor device models; semiconductor device reliability; CMOS technology; TCAD Sentaurus Synopsys simulator tool; drain bias; drain current degradation; gate oxide thickness; interface traps concentration; negative bias temperature instability; pMOSFET reliability; size 32 nm; technology CAD; threshold voltage; CMOS technology; Degradation; Equations; Hydrogen; MOSFET circuits; Niobium compounds; Stress; Temperature; Threshold voltage; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics (ICSE), 2010 IEEE International Conference on

Conference_Location

Melaka

Print_ISBN

978-1-4244-6608-5

Type

conf

DOI

10.1109/SMELEC.2010.5549578

Filename

5549578