Thermal budget optimization on Strained Silicon-On-Insulator (SSOI) CMOS

Author

Huang, R.M. ; Lin, Y.H. ; Tsai, S.H. ; Yang, C.W. ; Liu, E.C. ; Hsieh, Y.S. ; Cayrefourcq, Ian ; Tsai, C.T. ; Ma, G.H.

Author_Institution

United Microelectron. Corp. (UMC), Tainan

fYear

2008

Firstpage

118

Lastpage

119

Abstract

In this paper, we have systematically investigated the impact of the thermal-induced stress relaxation on biaxially strained silicon-on-insulator (SSOI) CMOS. We found that STI anneal would degrade nMOS drive current by 12% but improve pMOS by 17% in long channel SSOI devices. However, skipping LDD anneal would increase extension resistance and cause performance degradation. In addition, it is found that narrow-width devices suffer more serious thermal strain relaxation. After optimizing the thermal process, we successfully demonstrate enhanced sSOI nMOS with 65% transconductance gain at L = 1 um and 15% drive current improvement at L = 40 nm over SOI nMOS.

Keywords

CMOS integrated circuits; annealing; optimisation; silicon-on-insulator; thermal properties; SSOI; STI anneal; narrow-width device; performance degradation; strained silicon-on-insulator CMOS; thermal strain relaxation; Annealing; Capacitive sensors; Implants; MOS devices; Silicon on insulator technology; Tensile strain; Thermal degradation; Thermal resistance; Thermal stresses; Uniaxial strain;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530825

Filename

4530825