• DocumentCode
    1594921
  • Title

    Process-variation-tolerant zero skew clock routing

  • Author

    Lin, Shen ; Wong, C.K.

  • Author_Institution
    IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    1993
  • Firstpage
    83
  • Lastpage
    86
  • Abstract
    A new hierarchical two-stage multiple-merge zero skew clock routing algorithm is presented. The routing results produced by the approach will have zero skew and minimal skew increase in the worst process-variation situation
  • Keywords
    application specific integrated circuits; circuit layout CAD; clocks; delays; digital integrated circuits; integrated circuit layout; network routing; very high speed integrated circuits; ASIC; clock routing algorithm; hierarchical two-stage; high performance VLSI; multiple-merge; process-variation-tolerant; zero skew; Binary trees; Circuits; Clocks; Delay estimation; Electrical resistance measurement; Length measurement; Pins; Routing; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • Print_ISBN
    0-7803-1375-5
  • Type

    conf

  • DOI
    10.1109/ASIC.1993.410813
  • Filename
    410813
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1594921