On designing sigma-delta converter systems for class-D power amplifiers

The authors analyze sigma delta converters and present a method to design digitally driven class-D (PWM) amplifiers that achieve specific signal to noise ratios. This method allows a simple tradeoff between the order of the sigma delta converter and the increased sampling rate to be made to achieve the design goals. The authors demonstrate that this approach can be efficiently implemented in FPGAs and a modest DSP processor chip. This paper also presents a clarification and correction to the techniques proposed by Uchimura et al. (see IEEE Trans. Acoustics, Speech and Signal Processing, vol. 36, no. 12, pp. 1899-1905)