DocumentCode
1597809
Title
Efficient gate clustering for MTCMOS circuits
Author
Anis, Mohab H. ; Mahmoud, Mohamed K. ; Elmasry, Mohamed I.
Author_Institution
VLSI Res. Group, Waterloo Univ., Ont., Canada
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
34
Lastpage
38
Abstract
The problem, of, efficient gate clustering, in MTCMOS circuits is modeled as a bin-packing and set-partitioning problem. Both methodologies offer reduction in leakage power of up to 70% of previous techniques, while the latter takes routing complexity, into consideration. Satisfactory performance is achieved, with minimal area overhead
Keywords
CMOS logic circuits; bin packing; circuit layout CAD; leakage currents; logic CAD; logic gates; logic partitioning; network routing; CMOS logic; MTCMOS circuits; area overhead; bin-packing problem; efficient gate clustering; leakage power; multi-threshold CMOS; routing complexity; set-partitioning problem; CMOS technology; Circuits; Degradation; Logic gates; Resistors; Routing; Semiconductor device modeling; Sleep; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6741-3
Type
conf
DOI
10.1109/ASIC.2001.954669
Filename
954669
Link To Document