Energy dissipation in magnonic logic circuits

In this work, we provide a theoretical study on the energy dissipation in spin wave (magnonic) logic circuits. The circuits combine bi-stable multiferroic elements and ferromagnetic strips - spin wave buses. Power consumption is mainly defined by the efficiency of the multiferroic elements and the internal losses in the spin wave buses. Based on the available experimental data, we present the estimates on the energy per logic operation and project power dissipation in nanometer-scale magnonic circuits. According to the estimates, scaled magnonic logic circuits may consume as low as 10aJ per operation. We also present the estimates on the potential functional throughput enhancement and compare it with scaled CMOS.