Egress buffer performance optimisation for FR-ATM interworking

The implementation of FR-ATM network is presenting challenging service interworking issues. This paper describes the process of build-up delay in a FR ATM interworking, and proposes a new approach to reduce the latency by increasing the PIR/SIR ratio. Furthermore, a case study is introduced in order to validate the proposed method. Finally, the burstiness, virtual bandwidth and buffer overflow affecting the network performance are discussed.