A two-stage distributed shared memory architecture and its scheduling algorithms

Author

Peng, Yi ; Dong, Yuguo ; Wei, Jinwu ; Guo, Yunfei

Author_Institution

Nat. Digital Switching Syst. Eng. & Technol. R&D Center, Zhengzhou, China

Volume

1

fYear

2003

Firstpage

442

Abstract

The performance of a high-speed router is limited by the random access rate of memories and the switching rate of the inner switch architecture. This paper proposes a two-stage distributed shared memory architecture (TSDSM) and its scheduling algorithms which can emulate the FCFS and the PIFO output-queued (OQ) scheduling algorithms. The lower bound of the memories of the TSDSM is analyzed. We also prove that our algorithms can emulate the QQ scheduling algorithms. The most advantage of the TSDSM over other switching architectures is that the access rate of the memories is commercially available and the switch can work without speedup.

Keywords

distributed memory systems; memory architecture; shared memory systems; telecommunication switching; high-speed router; inner switch architecture; memory access rate; random access rate; scheduling algorithms; shared memory architecture; switching architecture; switching rate; two-stage distributed architecture; Acceleration; Bandwidth; Memory architecture; Packet switching; Read-write memory; Scheduling algorithm; Switches; Switching systems; Systems engineering and theory; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology Proceedings, 2003. ICCT 2003. International Conference on

Print_ISBN

7-5635-0686-1

Type

conf

DOI

10.1109/ICCT.2003.1209115

Filename

1209115